Session Name Titles 　 　 　 Authors 　 　 　 　 　 　 　 Affiliation 　 　 Country
　 Achieving Out-of-Order Performance with Almost In-Order Complexity Francis Tseng Yale N. Patt 　 ECE@Utexas USA
1 Novel Microarchitectures-Part I Fetch-Criticality Reduction through Control Independence Mayank Agarwal Nitin Navale Kshitiz Malik Matthew I. Frank 　 ECE@UIUC USA
　 　 A Two-Level Load/Store Queue Based on Execution Locality Miquel Pericas Adrian Cristal Francisco J. Cazorla Ruben Gonzalez Alex Veidenbaum Daniel A Jimenez Mateo Valero 　 　 　 BSC AC@UPC ICS@UCI CS@UTSA Spain
　 　 Self-Optimizing Memory Controllers: A Reinforcement Learning Approach Engin Ipek Onur Mutlu José Martínez Rich Caruana 　 　 　 　 　 　 Arch@MSR M3@Cornell 　 　 USA
2 Novel Memory Systems A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies Shyamkumar Thoziyoor Jung Ho Ahn Atteo Monchiero Jay B. Brockman Norm Jouppi 　 ECL@HP CSE@ND USA
　 　 Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems Onur Mutlu Thomas Moscibroda 　 　 　 　 　 　 　 　 SN@MSR 　 　 　 USA
　 　 Technology-Driven, Highly-Scalable Dragonfly Topology John Kim William J. Dally Steve Scott Dennis Abts 　 　 　 　 　 　 CVA@Standford Cray 　 　 USA
3 Interconnect Networks-Part I  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks Jae W. Lee Man Cheuk Ng Krste Asanović 　 SCALE@MIT USA
　 　 Polymorphic On-Chip Networks Martha Mercaldi Kim John D. Davis Mark Oskin Todd Austin 　 　 　 　 　 　 CS@Washington SV@MSR 　 　 USA
　 　 Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory Lee Baugh Naveen Neelakantam Craig Zilles 　 　 　 　 　 　 CS@UIUC 　 　 　 USA
4 Transactional Memory TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory Jayaram Bobba Neelam Goyal Mark D. Hill Michael M. Swift David A. Wood 　 CS@WISC USA
　 　 Flexible Decoupled Transactional Memory Support Arrvindh Shriraman Sandhya Dwarkadas Michael L. Scott 　 　 　 　 　 　 　 CS@Rochester 　 　 　 USA
　 　 Corona: System Implications of Emerging Nanophotonic Technology Dana Vantrease Robert Schreiber Matteo Monchiero Moray McLaren Norman P. Jouppi Marco Fiorentino Al Davis Nathan Binkert Raymond G. Beausoleil Jung Ho Ahn CS@WISC ECL@HP CS@Utah EECS@Umich USA
5 Emergent Technology Microcoded Architectures for Ion-Trap Quantum Computers Lucas Kreger-Stickles Mark Oskin 　 CS@Washington USA
　 　 Running a Quantum Circuit at the Speed of Data Nemanja Isailovic Mark Whitney Yatish Patel John Kubiatowicz 　 　 　 　 　 　 CS@Berkeley 　 　 　 USA
　 　 ReVIVaL: A Variation Tolerant Architecture using Voltage Interpolation and Variable Latency Xiaoyao Liang Gu-Yeon Wei David Brooks 　 　 　 　 　 　 EECS@Harvard 　 　 　 USA
6 Novel Microarchitectures-Part II Trading Off Cache Capacity for Reliability to Enable Low Voltage Operation Chris Wilkerson Hongliang Gao Alaa R. Alameldeen Zeshan Chishti Muhammad Khellah Shih-Lien Lu 　 MTL@Intel EECS@UCF USA
　 　 Counting Dependence Predictors Franziska Roesner Doug Burger Stephen W. Keckler 　 　 　 　 　 　 　 CS@Utexas 　 　 　 USA
　 　 Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support Natalie Enright Jerger Li-Shiuan Peh Mikko Lipasti 　 　 　 　 　 　 ECE@Wisc EE@Princeton 　 　 USA
7 Interconnect Networks-Part II iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures Avinash Karanth Kodi Ashwini Sarathy Ahmed Louri 　 EECS@Ohio ECE@Arizona USA
　 　 MIRA: A Multi-layer On Chip Interconnect Router Architecture Dongkook Park Soumya Eachempati Reetuparna Das Asit K. Mishra Yuan Xie N. Vijaykrishnan Chita R. Das 　 　 　 CSE@PSU 　 　 　 USA
　 　 Rerun: Exploiting Episodes for Lightweight memory Race Recording Derek R. Hower Mark D. Hill 　 　 　 　 　 　 　 CS@WISC 　 　 　 USA
8 Debugging Parallel Programs Atom-Aid: Detecting and Surviving Atomicity Violations Brandon Lucia Joseph Devietti Karin Strauss Luis Ceze 　 CS@Washington AATL@AMD USA
　 　 DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently Pablo Montesinos Luis Ceze Josep Torrellas 　 　 　 　 　 　 　 CS@UIUC CS@Washington 　 　 USA
　 　 Intra-Disk Parallelism: An Idea Whose Time Has Come Sriram Sankar Sudhanva Gurumurthi Mircea R. Stan 　 　 　 　 　 　 　 CS@Viginia ECE@Viginia 　 　 USA
9 System Architecture and I/O Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments Kevin Lim Parthasarathy Ranganathan Jichuan Chang Chandrakant Patel Trevor Mudge Steven Reinhardt 　 SEL@HP EECS@Umich USA
　 　 Improving NAND Flash Based Disk Caches Taeho Kgil David Roberts Trevor Mudge 　 　 　 　 　 　 　 EECS@Umich 　 　 　 USA
　 　 Online Estimation of Architectural Vulnerability Factor for Soft Errors Xiaodong Li Sarita V. Adve Pradip Bose Jude A. Rivers 　 　 　 　 　 　 CS@UIUC Watson@IBM 　 　 USA
10 Reliability A Proactive Wearout Recovery Approach of Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime Jeonghee Shin Victor Zyuban Pradip Bose Timothy M. Pinkston 　 CE@USC Watson@IBM USA
　 　 Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors Radu Teodorescu Josep Torrellas 　 　 　 　 　 　 　 　 CS@UIUC 　 　 　 USA
　 　 Flexible Hardware Acceleration for Instruction-Grain Program Monitoring Shimin Chen Michael Kozuch Theodoros Strigkos Babak Falsafi Phillip B. Gibbons Todd C. Mowry Vijaya Ramachandran Olatunji Ruwase Michael Ryan Evangelos Vlachos IRP@Intel CS@CMU 　 　 USA
11 Application Acceleration VEAL: Virtualized Execution Accelerator for Loops Nathan Clark Amir Hormati Scott Mahlke 　 EECS@Umich USA
　 　 From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware Haibo Chen Xi Wu Liwei Yuan Binyu Zang Pen-chung Yew Frederic T. Chong 　 　 　 　 PPI@Fudan CS@UMN CE@UCSB 　 China
　 　 Software-Controlled Priority Characterization of POWER5 Processor Carlos Boneti Francisco J. Cazorla Roberto Gioiosa Alper Buyuktosunoglu Chen-Yong Cher Mateo Valero 　 　 　 　 AC@UPC Watson@IBM 　 　 Spain
12 Performance Evaluation Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction Alex Shye Berkin Ozisikyilmaz Arindam Mallik Gokhan Memik Peter A. Dinda Robert P. Dick Alok N. Choudhary 　 　 　 EECS@NorthWestern 　 　 　 USA
　 　 Atomic Vector Operations on Chip Multiprocessors Sanjeev Kumar Daehyun Kim Mikhail Smelyanskiy Yen-Kuang Chen Jatin Chhugani Christopher J. Hughes Changyu Kim Victor W. Lee Anthony D. Nguyen 　 ARL@Intel 　 　 　 USA
13 Multi-core/Many-core Design 3D-Stacked Memory Architectures for Multi-Core Processors Gabriel H. Loh 　 　 　 　 　 　 　 　 　 3D@Gatech 　 　 　 USA